Patents:
1. Multiple gate tunneling field effect transistor device for capacitorless dynamic memory, A. Kranti, and N. Navlakha, Indian Patent 534756, 2024.
2. A method of fabricating zinc oxide based heterostructure for high electron mobility transistor, S. Mukherjee, A. Kranti, R. Singh, and Md. A. Khan, Indian Patent 490852, 2023.
3. Multiple gate junctionless MOSFET (Metal Oxide Semiconductor field effect transistor), A. Kranti and M. Gupta, Indian Patent 431061, 2023.
4. A method of fabricating high two dimensional electron gas density yielding zinc oxide heterostructure, S. Mukherjee, A. Kranti, Md.A. Khan, and R. Singh, Indian Patent 368230, 2021.
Publications:
2024:
1. Pragmatic evaluation of process corners in ULP subthreshold circuits with quantum confinement effects in junctionless nanowire transistor, N. Rai, S. Semwal, R.K. Nirala, and A. Kranti, IEEE Trans. Circuits and Systems-I , vol. 71, pp. 237-248, 2024.
2. Extremely high noise margin and low leakage in ULP circuits with NCFETs, S. Semwal, R.K. Nirala, M. Gupta, and A. Kranti, IEEE International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), Hsinchu, Taiwan, April 22-25, 2024, Accepted.
3. Energy and disturbance analysis of 1T-DRAM with nanowire gate-all-around RFET, R.K. Nirala, S. Semwal, M. Gupta, and A. Kranti, IEEE Trans. Electron Devices , vol. 71, pp. 2950-2956, 2024.
4. Quantum confinement imposed constraints in ULP circuits with junctionless FET, S. Semwal, N. Rai, R.K. Nirala, M. Gupta, and A. Kranti, IEEE Electron Devices Technology and Manufacturing (IEEE EDTM), Bengaluru, India, March 3-6, 2024, Accepted.
5. Disturbance induced refresh time lowering in nanowire RFET 1T-DRAM array, R.K. Nirala, M. Gupta, and A. Kranti, Extended Abstracts of the 2024 International Conference on Solid State Devices and Materials (SSDM), Himeji, Japan, September 1-4, 2024, pp. 629-630, 2024.
2023:
1. Architecture dependent constraint-aware RFET based 1T-DRAM, S. Semwal, R.K. Nirala, N. Rai, and A. Kranti, IEEE International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), Hsinchu, Taiwan, pp. 37-38, 2023.
2. Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications, R.K. Nirala, A.S. Roy, S. Semwal, N. Rai and A. Kranti, Japanese Journal of Applied Physics, vol. 62, SC1040, 2023.
3. Analytical modeling of negative capacitance transistor based ultra low power Schmitt trigger, G. Keerthi, S. Semwal, and A. Kranti, Solid-State Electronics, vol. 207, 108700, 2023.
4. Analytical modeling of architecture dependent atypical scaling trends in metal–Hf0.5Zr0.5O2–metal-SiO2–Si negative capacitance transistors, S. Semwal, and A. Kranti, Semiconductor Science and Technology, vol. 38, 095011, 2023.
5. Dual word line enabled energy-efficient high-speed RFET based 1T-eDRAM, A. Kranti, R.K. Nirala, and S. Semwal, Extended Abstracts of the 2023 International Conference on Solid State Devices and Materials (SSDM) , Nagoya, Japan, pp. 685-686, 2023.
6. Insights into parasitic capacitance and reconfigurable FET architecture for enhancing analog/RF metrics, A.A. Deshpande, S. Semwal, J.-P. Raskin, and A. Kranti, IEEE Trans. Electron Devices, vol. 70, pp. 5983-5990, 2023.
2022:
1. An insightful assessment of 1T-DRAM with misaligned polarity gate in RFET, A.S. Roy, S. Semwal and A. Kranti, IEEE Trans. Electron Devices, vol. 69, pp. 3163-3168, 2022.
2. Sensitivity implications for programmable transistor based 1T-DRAM, R.K. Nirala, S. Semwal, Y.V. Bhuvaneshwari, N. Rai and A. Kranti, Solid-State Electronics, vol. 194, 108353, 2022.
3. Unconventional VTC of subthreshold inverter with MFMIS negative capacitance transistor: An analytical modelling framework with implications for ultralow power logic design, S. Semwal and A. Kranti, Semiconductor Science and Technology, vol. 37, 065012, 2022.
4. Incorporating quantum effects in ultralow power (ULP) subthreshold logic design with junctionless nanowire transistor, N. Rai, K. Ahuja, S. Semwal and A. Kranti, IEEE Trans. Electron Devices, vol. 69, pp. 3983-3989, 2022.
5. Scalability and sensitivity assessment of programmable transistor based 1T-DRAM, R.K. Nirala, S. Semwal, Y.V. Bhuvaneshwari, N. Rai, and A. Kranti, 8th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), May 18-20, 2022, Accepted.
6. What are the constraints for 1T-DRAM operation via reconfigurable transistor?, R.K. Nirala, S. Semwal, N. Rai, and A. Kranti, 2022 International Conference on Solid State Devices and Materials (SSDM), September 26-29, 2022, Chiba, Japan, pp. 621-622, 2022.
7. A critique of length and bias dependent constraints for 1T-DRAM operation through RFET, R.K. Nirala, S. Semwal, and A. Kranti, Semiconductor Science and Technology, vol. 37, 105013, 2022.
2021:
1. Architecture dependent ferroelectric material considerations in planar and nanowire transistors, S. Semwal and A. Kranti, MRS Spring Meeting (Ferroelectricity and Negative Capacitance—Fundamentals, Applications and Controversies), April 18-23, EL09.14.04, 2021, Accepted.
2. Ferroelectric thickness dependent characteristics of negative capacitance transistors, S. Semwal and A. Kranti, 2021 IEEE International Symposium on Applications of Ferroelectrics (IEEE ISAF), May 16-21, 2021, Accepted.
3. Ultra-low power subthreshold logic with Germanium junctionless transistors, P. Shrivas, N. Jaiswal, S. Semwal and A. Kranti, Semiconductor Science and Technology, vol. 36, 075011, 2021.
4. Insights into unconventional behaviour of negative capacitance transistor through a physics-based analytical model, S. Semwal and A. Kranti, Semiconductor Science and Technology, vol. 36, 095018, 2021.
5. Improved mobility extraction methodology for reconfigurable transistors considering resistive components and effective drain bias, S. Mane, S. Semwal and A. Kranti, IEEE Trans. Electron Devices, vol. 68, pp. 4797-4800, 2021.
6. A metal-ferroelectric-insulator-semiconductor transistor perspective: Nanowire or planar architecture?, S. Semwal and A. Kranti, Journal of Materials Research, vol. 36, pp. 3484-3494, 2021. Invited Paper
7. Enhancing multi-functionality of reconfigurable transistors by implementing high retention capacitorless dynamic memory, Y.V. Bhuvaneshwari and A. Kranti, Semiconductor Science and Technology, vol. 36, 115003, 2021.
2020:
1. Junctionless Device Cross-Section: A Key Aspect for Overcoming Boltzmann Tyranny, A. Kranti and M. Gupta, 237th ECS Meeting – Advanced CMOS-Compatible Semiconductor Devices , Montreal, Canada, ECS Transactions, vol. 95, pp. 39-44, 2020. Invited Talk
2. Limits on hysteresis-free sub-60 mV/decade operation of MFIS nanowire transistor, S. Semwal, V.P. Reddy, N. Jaiswal and A. Kranti, IEEE Trans. Electron Devices, vol. 67, pp. 3868-3875, 2020.
2019:
1. Modeling short channel effects in core-shell junctionless MOSFET, N. Jaiswal and A. Kranti, IEEE Trans. Electron Devices, vol. 66, pp. 292-299, 2019.
2. 1T-DRAM with shell doped architecture, Md.H.R. Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, IEEE Trans. Electron Devices, vol. 66, pp. 428-435, 2019.
3. Optimization of multiple physical phenomena through a universal metric in junctionless transistors, M. Gupta and A. Kranti, In Proc. IEEE International Conference on VLSI Design, pp. 168-173, New Delhi, India, 2019.
4. Architecture evaluation for standalone and embedded 1T-DRAM, Md.H.R. Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), , Hsinchu, Taiwan, Accepted, 2019.
5. Raised body doping-less 1T-DRAM with source/drain Schottky contact, J.-T. Lin, W.-T. Sun, H.-H. Lin, Y.-J. Chen, N. Navlakha, and A. Kranti,, IEEE J. Electron Device Society, , vol. 7, pp. 276-281, 2019.
6. Gate-All-Around nanowire junctionless transistor based Hydrogen gas sensor, M. Siddharth, N. Jaiswal, M. Gupta, and A. Kranti, IEEE Sensors Journal, , vol. 19, pp. 4758-4764, 2019.
7. Improving charge retention in capacitorless DRAM through material and device innovation, M.H.R. Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, Japanese Journal of Applied Physics, vol. 58, SBBB03, 2019.
8. Estimation of doping in junctionless transistors through dc characteristics, Y.V. Bhuvaneshwari, and A. Kranti, Semiconductor Science and Technology, vol. 34, 055020, 2019.
9. Relevance of device cross-section to overcome Boltzmann switching limit in 3d junctionless transistor, M. Gupta, and A. Kranti, IEEE Trans. Electron Devices, vol. 66, pp. 2704-2709, 2019.
10. Bi-directional junctionless transistor for logic and memory applications, M. Gupta, and A. Kranti, IEEE Trans. Electron Devices, vol. 66, pp. 4446-4452, 2019.
11. Scalability and Vth Sensitivity Assessment of Core-Shell Junctionless MOSFET, N. Jaiswal, and A. Kranti, International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, pp. 653-654, 2019.
12. TFET based 1T-DRAM: Physics, sgnificance and trade-offs, N. Navlakha, Md.H.R. Ansari, and A. Kranti, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), San Jose, USA, Accepted, 2019.
2018:
1. Emerging FETs for low power and high speed embedded dynamic random access memory, Md. H.R. Ansari, N. Navlakha, J.-T. Lin and A. Kranti, IEEE International Conference on VLSI Design, pp. 422-472, Pune, India, 2018.
2. Hysteresis free sub-60 mV/dec subthreshold swing in junctionless MOSFETs, M. Gupta and A. Kranti, IEEE International Conference on VLSI Design, pp. 133-138, Pune, India, 2018.
3. Doping dependent assessment of accumulation mode and junctionless FET for 1T DRAM, Md.H.R. Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, IEEE Trans. Electron Devices, vol. 65, pp. 1205-1210, 2018.
4. A model for gate-underlap dependent short channel effects in junctionless MOSFET, N. Jaiswal, and A. Kranti, IEEE Trans. Electron Devices, vol. 65, pp. 881-887, 2018.
5. Dielectric modulated biosensor architecture: Tunneling or accumulation based transistor?, P. Dwivedi and A. Kranti, IEEE Sensors Journal, vol. 18, pp. 3228-3235, 2018.
6. Two dimensional electron gases in MgZnO/ZnO and ZnO/MgZnO/ZnO heterostructures grown by dual ion beam sputtering, R. Singh, Md.A. Khan, P. Sharma, M.T. Htay, A. Kranti and S. Mukherjee, Journal of Physics D: Applied Physics, vol. 51, 13LT02, 2018.
7. Raised source/drain Germanium junctionless MOSFET for sub-thermal off-to-on transition, M. Gupta and A. Kranti, IEEE Trans. Electron Devices, vol. 65, pp. 2406-2412, 2018.
8. Enhanced sheet charge density in DIBS grown CdO alloyed ZnO buffer based heterostructure, Md.A. Khan, R. Singh, R. Bhardwaj, A. Kumar, A.K. Das, P. Misra, A. Kranti, and S. Mukherjee, IEEE Electron Device Letters, vol. 39, pp. 827-830, 2018.
9. High retention with n-oxide-p junctionless architecture for 1T DRAM, Md.H.R. Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, IEEE Trans. Electron Devices, vol. 65, pp. 2797-2803, 2018.
10. Role of surface states and interface charges in 2DEG in sputtered ZnO heterostructure, R. Singh, Md.A. Khan, S. Mukherjee, and A. Kranti, IEEE Trans. Electron Devices, vol. 65, pp. 2850-2854, 2018.
11. Regaining switching by overcoming single transistor latch in Ge junctionless MOSFETs, M. Gupta, and A. Kranti, IEEE Trans. Electron Devices, vol. 65, pp. 3600-3607, 2018.
12. Modeling short channel effects in asymmetric junctionless MOSFETs with underlap, N. Jaiswal, and A. Kranti, IEEE Trans. Electron Devices, vol. 65, pp. 3669-3675, 2018.
13. Influence of material parameters on the performance of accumulation mode DRAM, Md.H.R. Ansari, N. Navlakha, J.-T. Lin and A. Kranti, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, 2018, Accepted.
14. 1T DRAM with vertically stacked n-oxide-p architecture, Md.H.R. Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, IEEE S3S Conference, San Francisco, USA, Accepted, 2018.
15. Performance assessment of TFET architectures as 1T-DRAM, N. Navlakha, Md.H.R. Ansari, J.-T. Lin, and A. Kranti, IEEE S3S Conference, San Francisco, USA, Accepted, 2018.
16. Physical insights on junction controllability for improved performance of planar trigate tunnel FET as capacitorless dynamic memory, N. Navlakha, and A. Kranti, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Austin, USA, Accepted, 2018.
17. Effects of bulk-defects and metal/bulk interface anomalies in a forming-free double-barrier memristor, A. Kumar, S. Mukherjee, and A. Kranti, Journal of Physics D: Applied Physics, vol. 51, 405601, 2018.
18. Overcoming biomolecule location dependent sensitivity degradation through point and line tunneling in dielectric modulated biosensors, P. Dwivedi and A. Kranti, IEEE Sensors Journal, vol. 18, pp. 9604-9611, 2018.
19. Assessment of mobility and its degradation parameters in shell doped junctionless transistor, Y.V. Bhuvaneshwari and A. Kranti, Semiconductor Science and Technology, vol. 33, 115020, 2018.
2017:
1. Steep switching Germanium junctionless MOSFET with reduced off-state tunneling, M. Gupta and A. Kranti, IEEE Trans. Electron Devices, vol. 64, pp. 3582-3587, 2017.
2. Analytical model for 2DEG density in graded MgZnO/ZnO heterostructures with cap layer, R. Singh, Md. A. Khan, S. Mukherjee and A. Kranti, IEEE Trans. Electron Devices, vol. 64, pp. 3661-3667, 2017
3. Hysteresis free negative total gate capacitance in junctionless transistors, M. Gupta, and A. Kranti, Semiconductor Science and Technology, vol. 32, 095014, 2017.
4. Variation of threshold voltage with temperature in impact ionization induced steep switching Si and Ge junctionless MOSFETs, M. Gupta and A. Kranti, IEEE Trans. Electron Devices, vol. 64, pp. 2061-2066, 2017.
5. Retention and scalability perspective of sub-100 nm double gate tunnel FET DRAM, N. Navlakha, J.-T. Lin, and A. Kranti, IEEE Trans. Electron Devices, vol. 64, pp. 1561-1567, 2017.
6. Insights into operation of planar tri-gate tunnel field effect transistor for dynamic memory application, N. Navlakha, and A. Kranti, Journal of Applied Physics, vol. 122, 044502, 2017.
7. Applicability of transconductance-to-current ratio (gm/Ids) as a sensing metric for tunnel FET biosensors, P. Dwivedi and A. Kranti, IEEE Sensors Journal, vol. 17, pp. 1030-1036, 2017.
8. A new electron bridge channel 1T-DRAM emplying underlap region charge storage, J.-T. Lin, W.-H. Lee, P.-H. Lin, S.W. Haga, Y.-R. Chen and A. Kranti, IEEE Journal of Electron Device Society, vol. 5, pp. 59-63, 2017.
9. Forming-free high-endurance Al/ZnO/Al memristor fabricated by dual ion beam sputtering, A. Kumar, M. Das, V. Garg, B.S. Sengar, M.T. Htay, S. Kumar, A. Kranti, and S. Mukherjee, Applied Physics Letters, vol. 110, 253509, 2017.
10. Insights into operation of planar tri-gate tunnel field effect transistor for dynamic memory application, N. Navlakha, and A. Kranti, Journal of Applied Physics, vol. 122, 044502, 2017.
11. Extraction of mobility and degradation coefficients in double gate junctionless transistors, Y.V. Bhuvaneshwari and A. Kranti, Semiconductor Science and Technology, vol. 32, 125011, 2017.
12. Buffer layer engineering for high (> 1013 cm-3) 2DEG density in ZnO based heterostructures, Md. A. Khan, R. Singh, S. Mukherjee and A. Kranti, IEEE Trans. Electron Devices, vol. 64, pp. 1015-1019, 2017.
13. Vertical transistor with n-bridge and body on gate for low power 1T-DRAM application, J.-T. Lin, H.-H. Lin, Y.-J. Chen, C.-Y. Yu, A. Kranti, C.-C. Lin and W.-H. Lee, IEEE Trans. Electron Devices, vol. 64, pp. 4937-4945, 2017.
14. Design optimization of tunnel FET for dynamic memory applications, N. Navlakha, J.-T. Lin, and A. Kranti, In Proc. IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, Taiwan, 2017.
15. Steep current transition in germanium junctionless transistor, M. Gupta and A. Kranti, In Proc. IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, Taiwan, 2017.
16. Twin gate Tunnel FET based capacitorless dynamic memory, N. Navlakha, J.-T. Lin, and A. Kranti, In Proc. International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) , Hsinchu, Taiwan, 2017.
2016:
1. Investigation of barrier inhomogeneities and interface state density in Au/MgZnO:Ga Schottky contact, R. Singh, Md. A. Khan, V. Garg, V. Awasthi, A. Kranti and S. Mukherjee, Journal of Physics D: Applied Physics, vol. 49, 445303, 2016.
2. Transforming gate misalignment into a unique opportunity to facilitate steep switching in junctionless transistors, M. Gupta, and A. Kranti, Nanotechnology, vol. 27, 455204, 2016.
3. Improved retention time in twin gate 1T DRAM with tunneling based read mechanism, N. Navlakha, J.-T. Lin, and A. Kranti, IEEE Electron Device Letters, vol. 39, pp. 1127-1130, 2016.
4. Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering, N. Navlakha, J.-T. Lin, and A. Kranti, Journal of Applied Physics, vol. 119, 214501, 2016.
5. Sidewall spacer optimization for steep switching junctionless transistors, M. Gupta and A. Kranti, Semiconductor Science and Technology, vol. 31, 065017, 2016.
2015:
1. Impact of channel doping and spacer architecture on analog/RF performance of low power junctionless MOSFETs, D. Ghosh, and A. Kranti, Semiconductor Science and Technology, vol. 30, 015002, 2014.
2. Germanium junctionless MOSFET with steep subthreshold swing, M. Gupta, and A. Kranti, In Proc. 227th ECS Meeting, International Symposium on Advanced CMOS Compatible Semiconductor Devices, Chicago, USA, In Proc. ECS Trans., vol. 66, no. 5, pp. 79-86, 2015.
3. Enhanced sensitivity of junctionless transistor architecture for biosensing applications, M.S. Parihar and A. Kranti, Nanotechnology, vol. 26, 145201, 2015.
2014:
1. Revisiting the doping requirement for low power junctionless MOSFETs, M.S. Parihar, and A. Kranti, Semiconductor Science and Technology, vol. 29, 075006, 2014.
2. Back bias induced dynamic and steep subthreshold swing in junctionless transistors, M.S. Parihar, and A. Kranti, Applied Physics Letters, vol. 105, 033503, 2014.
3. Performance assessment of ULP analog/RF MOSFET architectures, D. Ghosh and A. Kranti, In Proc. IEEE S3S Conference, California, USA, Accepted, 2014.
4. Junctionless composite transistor for ultra low power logic applications, A. Kumar, M.S. Parihar, and A. Kranti, In Proc. IEEE International Nanoelectronics Conference (INEC), Sapporo, Japan, Accepted, 2014.
5. Junctionless transistors for dynamic memory and sensing applications, M.S. Parihar, and A. Kranti, In Proc. IEEE International Nanoelectronics Conference (INEC), Sapporo, Japan, Accepted, 2014.
6. Volume accumulated double gate junctionless MOSFETs for low power logic technology applications, M.S. Parihar, and A. Kranti, In Proc. IEEE International Symposium on Quality Electron Design, Santa Clara, USA, pp. 335-340, 2014.
7. Performance optimization and parameter sensitivity analysis of ultra low power junctionless MOSFETs, M.S. Parihar, and A. Kranti, In Proc. International Conference on VLSI Design, Mumbai, pp. 439-443, 2014.
2013:
1. Single transistor latch phenomenon in junctionless transistors, M.S. Parihar, D. Ghosh, and A. Kranti, Journal of Applied Physics, vol. 113, 184503, 2013.
2. Ultra low power junctionless MOSFETs for subthreshold logic applications, M.S. Parihar, D. Ghosh, and A. Kranti, IEEE Trans. Electron Devices, vol. 60, no. 5, pp. 1540-1546, 2013.
3. Occurrence of zero gate oxide thickness coefficient in junctionless transistors, M.S. Parihar, D. Ghosh, and A. Kranti, Applied Physics Letters, vol. 102, 203509, 2013.
4. Single transistor latch phenomena in junctionless nanotransistors, M.S. Parihar, D. Ghosh, G.A. Armstrong and A. Kranti, In Proc. IEEE International Nanoelectronics Conference (INEC), Singapore, pp. 72-73, 2013.
5. Optimizing nanoscale MOSFET architecture for low power analog/RF applications, D. Ghosh, M.S. Parihar and A. Kranti, In Proc. IEEE International Nanoelectronics Conference (INEC), Singapore, pp. 22-23, 2013.
6. RF performance of ultra low power junctionless MOSFETs, D. Ghosh, M.S. Parihar and A. Kranti, In Proc. Asia Pacific Microwave Conference, Seoul, pp. 787-789, 2013.
7. Bipolar attributes of unipolar junctionless MOSFETs, M.S. Parihar and A. Kranti, In Proc. International Workshop on Physics of Semiconductor Devices (IWPSD), pp. 169-170, 2013.
2012:
1. Device design and estimated performance for p-type junctionless transistors on bulk germanium substrates, R. Yu, S. Das, I. Ferain, P. Razavi, M. Shayesteh, A. Kranti, R. Duffy and J.P. Colinge, IEEE Trans. Electron Devices, vol. 59, no. 9, pp. 2308- 2313, 2012.
2. High performance junctionless MOSFETs for ultra low power analog/RF applications, D. Ghosh, M.S. Parihar, G.A. Armstrong and A. Kranti, IEEE Electron Device Letters, vol. 33, no. 10, pp. 1477-1479, 2012.
3. Bipolar effects in unipolar junctionless transistors, M.S. Parihar, D. Ghosh, G.A. Armstrong, R. Yu, P. Razavi and A. Kranti, Applied Physics Letters, vol. 101, 903507, 2012.
4. Bipolar snapback in junctionless transistors for capacitorless dynamic random access memory, M.S. Parihar, D. Ghosh, G.A. Armstrong and A. Kranti, Applied Physics Letters, vol. 101, 263503, 2012.
5. Optimally designed moderately inverted double gate SOI MOSFETs for low-power RFICs, Dipankar Ghosh, Mukta Singh Parihar, G. Alastair Armstrong, and A. Kranti, Semiconductor Science and Technology, vol. 27, 125004, 2012.
6. Sensitivity Analysis of steep Subthreshold Slope (S–slope) in Junctionless Nanotransistors, M.S. Parihar, D. Ghosh, G.A. Armstrong, R. Yu, P. Razavi, S. Das, I. Ferain, and A. Kranti, In Proc. IEEE International Conference on Nanotechnology, Birmingham, UK, 2012.
7. Low Power Nanoscale RF/Analog MOSFETs, D. Ghosh, M.S. Parihar, G.A. Armstrong and A. Kranti, In Proc. IEEE International Conference on Nanotechnology, Birmingham, UK, 2012.
2011:
1. Junctionless nanowire transistor: complementary metal-oxide-semiconductor without junctions, J.-P. Colinge, I. Ferain, A. Kranti, C.-W. Lee, N. Akhavan, P. Razavi, R. Yan and R. Yu, Science of Advanced Materials, vol. 3, no. 3, pp. 1–6, 2011.
2. Influence of elastic and inelastic electron–phonon interaction on quantum transport in multigate silicon nanowire MOSFETs, N. Akhavan, A. Afzalian, A. Kranti, I. Ferain, C.-W. Lee, R. Yan, P. Razavi, R. Yu and J.-P. Colinge, IEEE Trans. Electron Devices, vol. 58, no. 4, pp. 1029-1037, 2011.
3. Investigation of high-performance sub-50 nm junctionless nanowire transistors, R. Yan, A. Kranti, I. Ferain, C.-W. Lee, R. Yu, N. Akhavan, P. Razavi and J.-P. Colinge, Microelectronics Reliability, vol. 51, no. 7, pp. 1166-1071, 2011.
4. Junctionless multiple-gate transistors for analog applications, R.D. Doria, M.A. Pavanello, R.D. Trevisoli, M. de Souza, C.-W. Lee, I. Ferain, N.D. Akhavan, R. Yan, P. Razavi, R. Yu, A. Kranti and J.-P. Colinge, IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2511 – 2519, 2011.
5. Extraction of channel mobility in nanowire MOSFETs using Id(Vg) characteristics and random telegraph noise amplitude, A.N. Nazarov, C.W. Lee, A. Kranti, I. Ferain, R. Yan, N. Akhavan, P. Razavi, R. Yu and J.-P. Colinge, In Proc. Ultimate Integration on Silicon (ULIS), Cork, Ireland, pp. 107-109, 2011.
6. Junctionless transistors: physics and properties, J.P. Colinge, C.W. Lee, N. Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti and R. Yu, In Proc. International Semiconductor-on-Insulator Workshop on Nanoscaled Semiconductor-on-Insulator Materials, Sensors and Devices, Kyiv, Ukraine, pp. 187-200, 2011.
7. Comparative study of random telegraph noise in junctionless and inversion-mode MuGFETs, A.N. Nazarov, C.W. Lee, A. Kranti, I. Ferain, R. Yan, N. Akhavan, P. Razavi, R. Yu, J.P. Colinge, In Proc. ECS Transactions: 219th ECS Meeting on Advanced Silicon-on-Insulator Technology and Related Physics, Montreal, Canada, vol. 35, no. 5, pp. 73-78, 2011.
8. The roles of the electric field and the density of carriers in the improved output conductance of junctionless nanowire transistors, R.T. Doria, M.A. Pavanello, R.D. Trevisoli, M. Souza, C.W. Lee, I. Ferain, N. Akhavan, R. Yan, P. Razavi, R. Yu, A. Kranti and J.P. Colinge, In Proc. ECS Transactions: 219th Meeting on Advanced Silicon-on-Insulator Technology and Related Physics, Montreal, Canada, vol. 35, no. 5, pp. 283-288, 2011.
9. A simulation comparison between junctionless and inversion-mode MuGFETs, J.P. Colinge, A. Kranti, R. Yan, I. Ferain, N. Akhavan, P. Razavi, C.W. Lee, R. Yu and C.A. Colinge, In Proc. ECS Transactions: 219th ECS Meeting on Advanced Silicon-on-Insulator Technology and Related Physics, Montreal, Canada, vol. 35, no. 5, pp. 63-72, 2011.
10. Source/Drain Engineered Ultra Low Power Analog/RF UTBB MOSFET, A. Kranti, J.-P. Raskin and G.A. Armstrong, In Proc. Ultimate Integration on Silicon (ULIS), Cork, Ireland, Digital Object Identifier: 10.1109/ULIS.2011.5757997, 2011.
11. Analytical model for the threshold voltage of junctionless nanowire transistors, R. D. Trevisoli, M. A. Pavanello, R. T. Doria, M. de Souza, C.W. Lee, I. Ferain, N. Dehdashti Akhavan, R. Yan, P. Razavi, R. Yu, A. Kranti and J.P. Colinge, In Proc.Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EuroSOI), Granada, Spain, pp. 67-68, 2011.
12. Extraction of flat-band voltage and parasitic resistance in junctionless MuGFETs, A.N. Nazarov, C.W. Lee, A. Kranti, I. Ferain, R. Yan, N. Dehdashti Akhavan, P. Razavi, R. Yu, JP Colinge, In Proc. Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EuroSOI), Granada, Spain, pp. 53-54, 2011.