PEER REVIEWED PUBLICATIONS

• International Journals

  1. V K Mishra, Anirban Sengupta, Swarm Inspired Exploration of Architecture and Unrolling Factors for Nested Loop Based Application in Architectural Synthesis, IEEE (IET) Electronics Letters, Accepted, Dec 2014
  2. Anirban Sengupta, Vipul Kumar Mishra " Automated Exploration of Datapath and Unrolling Factor during Power-Performance Tradeoff in Architectural Synthesis Using Multi-Dimensional PSO Algorithm " , Elsevier Journal on Expert Systems With Applications, UK,Volume 41, Issue 10, Pages 4691-4703, August 2014(5yr Impact Factor = 2.339).
  3. Vipul Kumar Mishra, Anirban Sengupta, " MO-PSE: Adaptive Multi Objective Particle Swarm Optimization Based Design Space Exploration in Architectural Synthesis for Application Specific Processor Design ", Elsevier Journal on Advances in Engineering Software, Volume 67, Issue: C, pp. 111–124, January 2014
  4. Anirban Sengupta, Vipul Mishra. Simultaneous Exploration of Optimal Datapath and Loop Based High level Transformation during Area-Delay Tradeoff in Architectural Synthesis Using Swarm Intelligence, IOS Press, Journal of Knowledge-Based and Intelligent Engineering Systems, Volume 19, April 2015, pp. 47 - 61, 2015.
  5. Anirban Sengupta, Reza Sedaghat, Vipul Kumar Mishra, " Execution Time Area Tradeoff in GA using Residual Load Decoder: Integrated Exploration of Chaining Based Schedule and Allocation in HLS for Hardware Accelerators ", Journal of Electronics and Energetics: Facta Universitatis, Volume 27, No. 2,pp. 235-249,June 2014. (Impact Factor = 0.6) (INVITED PAPER)
  6. Anirban Sengupta, Vipul Kumar Mishra, “A Methodology for Comprehensive Schedule Delay Estimation during Design space Exploration in Architectural Synthesis, IEEE VLSI Circuits & Systems Letter (Letter of TCVLSI), Volume 1, Issue 1, April 2015, pp. 2 - 8.

• International Conferences

  7. Vipul Mishra, Anirban Sengupta, PSDSE: Particle Swarm Driven Design Space Exploration of Architecture and Unrolling Factors for Nested Loops in High Level Synthesis?, Accepted, Proceedings of 5th IEEE International Symposium on Electronic Design (ISED),Dec 2014, pp. 10 - 14(DOUBLE BLIND REVIEW).
  8. Vipul Mishra, Anirban Sengupta "Swarm Intelligence Driven Design Space Exploration: An Integrated Framework for Power-Performance Trade-off in Architectural Synthesis ", Proceedings of 25th IEEE International Conference on Microelectronics (ICM 2013), September 2013. pp. 1-4
  9. Anirban Sengupta, Vipul Kumar Mishra, " Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff ", Proceedings of 13th IEEE Computer Society Annual International Symposium on VLSI (ISVLSI), Florida, USA, July 2014, pp. 106 112 (BLIND REVIEW).
  10. Anirban Sengupta, Vipul Kumar Mishra , " Integrated Particle Swarm Optimization (i-PSO): An Adaptive Design Space Exploration Framework for Power-Performance Tradeoff in Architectural Synthesis ", Proceedings of IEEE 15th International Symposium on Quality Electronic Design (ISQED 2014), Santa Clara, California, USA, March 2014, pp.60 - 67 (BLIND REVIEW).
  11. Anirban Sengupta, Vipul Mishra, " Automated Parallel Exploration of Datapath and Unrolling Factor in High Level Synthesis using Hyper-Dime?nsional Particle Swarm Encoding ", Proceedings of 27th IEEE Canadian Conference on Electrical and Computer Engineering, Toronto, May 2014, pp. 069 - 073.
  12. Anirban Sengupta and Vipul Kumar Mishra, "Time Varying vs. Fixed Acceleration Coefficient PSO Driven Exploration during High Level Synthesis: Performance and Quality ", Proceedings of 13th IEEE International Conference on Information Technology, Dec 2014, pp. 281 - 286 (DOUBLE BLIND REVIEW).
  13. Anirban Sengupta, Vipul Kumar Mishra, Pallabi Sarkar, "Rapid Search of Pareto Fronts using D-logic Exploration during Multi-Objective Tradeoff of Computation Intensive Applications ", Proceedings of IEEE 5th Asian Symposium on Quality Electronic Design (ASQED), Malaysia, pp. 113-122, August 2013.
  14. Anirban Sengupta, Vipul Mishra, "D-logic Exploration: Rapid Search of Pareto Fronts during Architectural Synthesis of Custom Processors", IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI-2013), Mysore, pp. 586 - 593, August 2013.
  15. Mishra, V.K.; Mehta, D.A., "Performance enhancement of NUMA multiprocessor systems with on-demand memory migration," IEEE 3rd International conference on Advance Computing Conference (IACC), 2013, vol., no., pp.40-43
  16. Anirban Sengupta, Vipul Mishra, Multidimensional Encoding Based Evolutionary Exploration Approach: Adaptive Methodology for Parametric Trade-offs in High Level Synthesis for Control flow Graphs?, Proceedings of 3rd IEEE CALCON, Nov 2014, pp. 43- 46

• Poster

  17. Poster presentation on " A High level Synthesis Design Flow ESL to RTL " in 2nd industry academia conclave 2013 held in Indian institute of Technology Indore.
  18. Poster presentation on "Swarm Inspired Design Space Exploration in High Level Synthesis" in 3rd industry academia conclave 2014 held in Indian institute of Technology Indore.